1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatus for programmable and/or scalable terminations within integrated circuits.
2. Background
As the speed of transmission lines included in memory interfaces and buses increases, impedance “matching” become increasingly important. The characteristic impedance of a transmission line is the ratio of voltage to current of a signal moving along the transmission line. By terminating the transmission line with a load (e.g., an impedance) equal to the characteristic impedance of the transmission line, a signal pulse applied to the transmission line is transferred to the load without reflection. The benefits of impedance matching, such as reduced signal reflection and signal loss during signal transmission, are well known to one of skill in the art and is not be described further herein.
FIG. 1 is a diagram of a conventional programmable termination circuit 100. The programmable termination circuit 100 includes an impedance evaluation control circuit 102 coupled to a resistive element 104. The resistive element 104 is coupled to a port 106 included in a memory system (not shown). The port 106 may correspond to a transmission line included in a bus for the memory system, or a memory interface, for example.
The resistive element 104 includes an upper portion 108 of circuitry including a plurality of p-channel metal-oxide semiconductor field-effect transistors (PFETs) P0-P7 connected in parallel between a high voltage level (e.g., VDDQ) and the port 106. The PFET P0 is a default device that is always on and determines (along with NFET N0) the maximum impedance that may be created by the resistive element 104. The PFETs P1-P7 are arranged in size order such that PFET P1 is the narrowest transistor and PFET P7 is the widest transistor.
The resistive element 104 includes a lower portion 110 of circuitry including a plurality of n-channel metal-oxide semiconductor field-effect transistors (NFETs) N0-N7 connected in parallel between the port 106 and ground. The NFET N0 is a default device that is always on and determines (along with PFET P0) the maximum impedance that may be created by the resistive element 104. The NFETs N1-N7 are arranged in size order such that NFET N1 is the narrowest transistor and NFET N7 is the widest transistor.
The upper portion 108 of circuitry is connected in series with the lower portion 110 of circuitry to create a voltage divider that provides a termination for a signal output from circuitry that employs the programmable termination circuit 100. The terminated impedance is created by the resistive element 104, on the port 106. Each PFET, NFET combination (e.g., P0-N0, P1-N1, P2-N2, etc.) is referred to herein as a stacked transistor pair. However, it should be understood that each of the transistors PFETs P1-P7 and NFETs N1-N7 may operate independently.
The impedance evaluation control logic 102 outputs a fixed set of control or binary termination signals (e.g., binary counts) p1-p7 and n1-n7 to the PFETs P1-P7 and NFETs N1-N7, respectively, for selectively activating or de-activating the transistors (thereby creating a resistive element 104 of a fixed impedance (e.g., once programmed via the impedance evaluation control logic 102 described below with reference to FIG. 2), which is used for outputting a signal on the port 106). In one embodiment, the most significant bit of a binary count is provided to the widest transistor, and the least significant bit is provided to the narrowest transistor. As stated, because the default devices P0, N0 are always on, the default devices P0, N0 sets the maximum impedance value of the resistive element 104.
FIG. 2 is a diagram of the conventional impedance evaluation control circuit 102 of FIG. 1. The impedance evaluation control circuit 102 may include control logic 202 coupled to a plurality 204 of PFETs 204a-h connected in parallel between a high voltage level (e.g., VDDQ) and a port 206 (e.g., a chip pad) included, for example, in a memory system (not shown). The PFETs 204a-h may be arranged in size order in a manner similar to the PFETs P1-P7 included in the upper portion 108 of the resistive element 104 of FIG. 1.
The control logic 202 may be coupled to the port 206 via a feedback line 208. A resistor 210 (e.g., an external resistor connected to a system board) is coupled between the port 206 and ground. Consequently, the impedance evaluation control circuit 102 acts as a voltage divider.
The control logic 202 outputs bits of a binary count signal (e.g., signals p1-p7) to the plurality 204 of PFETs 204a-h, respectively, and in response thereto receives a value indicating the voltage at the port 206 via the feedback line 208. In one embodiment, the most significant bit of the binary count signal is provided to the widest transistor, and the least significant bit is provided to the narrowest transistor. The control logic 202 compares the voltage at the port 206 with a reference voltage (e.g., a desired value such as VDDQ/2) included in the control logic 206 and outputs a different binary count signal until the voltage at port 206 matches the reference voltage (e.g., VDDQ/2). Once the voltage at port 206 matches the reference voltage, the impedance evaluation control circuit 102 fixes and outputs the binary count (e.g., control signals p1-p7) used for creating the voltage at port 206 to the PFETs P1-P7 of FIG. 1. Although not shown in FIG. 2, the impedance evaluation control circuit 102 may create control signals n1-n7 in a similar manner and provide the same to the NFETs N1-N7 of FIG. 1. In this manner, the impedance evaluation control circuit 102 generates control or binary termination signals p1-p7, n1-n7 used for creating a resistive element 104 (e.g., terminator) of a fixed impedance (e.g., the characteristic impedance) based on the value of the external resistor 210. Thus, the conventional impedance evaluation control circuit 102 determines a characteristic impedance of a port by generating a plurality of binary termination signals.
Different applications and different types of signals corresponding to an application, such as data, address, and/or clock signals, may require different termination values for optimal transmission. Although a different programmable termination circuit 100 may be used for creating the required termination value for each different port of an application (e.g., a memory system) such a solution requires the above circuitry for each port.